The present invention relates to a method of encoding data to be recorded in a recording and reproducing apparatus for encoding the data and recording the same in a recording medium, and performing reproduction and decoding thereof, and a signal processing method for obtaining error-reduced decoded data from a reproduced signal, and to a circuit thereof.
There has been an increasingly growing demand for high recording densification to a recording and reproducing apparatus, e.g., a magnetic disk device or hard disk drive (hereinafter called HDD) or the like. A signal processing technique of a recording and reproduction system that supports it has also been adapted to the high recording densification.
FIG. 2 shows one example of a data recording and reproducing processing circuit employed in the conventional HDD. In FIG. 2, recording data inputted to an input terminal 1 is subjected to error correction encoding by a symbol error correction encoder 10 on the recording side. The Reed-Solomon code (hereinafter called RS code) is often used as an error correcting code. Further, the signal is added with parity bits by a parity encoder 21 (it might be omitted). The signal is added with a sync signal or the like by a recording processing circuit 30, after which information is recorded in a recording medium 60 via a recording amplifier 40 and a recording head 50.
On the reproduction side, the signal read from the recording medium 60 by a reproducing head 150 is amplified by a reproducing amplifier 140. A reproducing processing circuit 130 effects sync signal detection or the like on the signal and inputs the so-processed signal to a parity decoder 121. The parity decoder 121 corrects a random error, using likelihood information and parities. Thereafter, a symbol error correction decoder 110 performs the correction of a code error such as a burst error due to a defect produced upon recording and playback and outputs the corrected signal to an output terminal 2.
A magnetic recording channel has a frequency response which can be made approximate by one in which a differential unit and a low-pass filter are connected in series. Assuming that D is defined as a delay operator at one time, the magnetic recording channel is configured such that interference among codes thereof is modeled as a partial response channel having an impulse response of (1−D)(1+D)n (where n=1, 2, 3, . . . ).
In order to cope with such a channel, a Viterbi decoder is used for the reproducing processing circuit 130. The Viterbi decoder is used to carry out a maximum likelihood estimation of a transmission sequence in a band-restricted channel having code-to-code interference. That is, a code sequence for minimizing a distance metric related to the sequence of a received signal, such as the sum of square errors in the received signal sequence, for example, is selected from possible code sequences.
Conway, “A new target response with parity coding for high density magnetic recording channels,” (1998) IEEE Trans. Magn, 34(4), pp. 2382-2386, has proposed a method of adding parity codes in fine cycles to correct random errors and correcting it using the parity information and likelihood information of a reproduced signal upon reproduction.
The parity correcting method was accompanied by the problem that an increase in the amount of recorded data and an increase in random error due to the speeding up of a data transfer rate could not be completely corrected, thus making it unable to ensure sufficient performance.
The Shannon limit given by the so-called Shannon's channel encoding theorem is known as a theoretical limit to code performance. Examples of an encoding method indicating the performance close to the Shannon limit include a coding/decoding method using Parallel Concatenated Convolutional Codes called turbo coding/decoding, which has been described in, for example, U.S. Pat. No. 5,446,747 (columns 7-10 and FIGS. 1-4). This will be described briefly here.
Encoding using the parallel concatenated convolutional codes is done by a device wherein two of a convolutional encoder and an interleaver are configured in parallel in concatenated form. Decoding of the parallel concatenated convolutional codes is performed by a device configured of two decoding circuits each of which outputs a soft-output. A transfer of information is performed between the two decoding circuits, whereby the final result of decoding is obtained.
There has also been known an encoding method using cascade concatenated convolutional codes without using the parallel concatenation. A method of combining the cascade concatenated convolutional codes with the RS code to thereby perform an error correction has been proposed in Japanese Patent Laid-open No. 2001-285080 (pages 9-11 and FIGS. 6 through 9). In this document, a modulation scheme for performing cascade concatenated convolutional coding for an internal code has been adopted for data subjected to RS coding as an external code. As to decoding, two-stage decoding of cascade concatenated codes is carried out. Thereafter, RS decoding is done. At this time, a determination unit for determining whether errors contained in decoded data exist in some degree, determined whether a lost correction should be done according to the determined reference (some of errors), outputted a lost flag to an RS decoder, and made a decision as to whether the normal error correction should be done according to the presence or absence of the lost flag or the lost correction should be done.
However, the parallel concatenated convolutional coding/decoding method and the cascade concatenated decoding method need redundant signals (redundant bits) for realizing the convolutional coding modulation scheme. As a result, a code rate loss occurs inevitably, and hence the total performance could not be enhanced sufficiently.